Power Supply Sequencing 2

"Early into reading this paper a sickness struck me in the pit of the stomach and stayed with me to the end."

If for some reason you thought that power sequencing is a trivial problem, reading this paper will give you a good idea of the complexities. The authors of Sequencing Power Supplies in Multiple Voltage Rail Environments in the Texas Instruments 2004/05 Power Supply Design Seminar provide an excellent explanation of why turn-on and turn-off sequencing is necessary, the types of sequencing, and a variety of solution examples. This information is in 31 compact pages.

The paper shows many examples of power sequencing implemented with:

• Diodes
• Low-dropout (LDO) linear regulators
• Supply voltage supervisors (SVS)
• Power distribution switches
• Hot-swap controllers
• Microcontrollers
• Switch-mode controllers (power FETs external)
• Switch-mode converters (power FETs internal)
• Plug-in power modules

The paper does an outstanding job of explaining problems and current solutions. Never-the-less early into reading this paper a sickness struck me in the pit of the stomach and stayed with me to the end. This had nothing to do with the excellence of the paper - which is outstanding. However, the paper brought home the fact that the digital designers appear to be winning the decades-long battle of pushing difficult design problems out of their integrated circuits and into the hands of everybody else. In this case, the need to sequence power supplies for reliability purposes and for a variety of non-critical purposes.

Now don't get me wrong. Much of my career has been in designing power supplies for digital computers and I am well aware of the need to sequence certain critical circuits to cleanly turn the computer on into a known initial state and the need to sequence power off to prevent wild things happening to the I/O circuits. But things have gone too far when sequencing is required by circuits that may not be critical to these tasks or to prevent reliability damage or failure of circuits if not sequenced properly.

My early experience was designing power supplies to survive and recover a nuclear bomb blast. Now that is a severe environment! The air around the circuits is ionized into a conductive gas for a brief period of time. Imagine dipping your operating circuit into a pool of mercury and pulling it out and being required to have it still work like nothing happened. In addition, primary photo-current generators inherent in each semiconductor junction generate currents approaching hundreds of amperes in circuits normally operating in the sub milliampere range. Every junction becomes a short for a brief period of time and then things return to normal in a totally unsequenced way. And that unsequenced recovery could not degrade the reliability of the circuit. Harsh? Yes, but harsh things also happen when a fuse is blown or an output shorted. You really don't want a momentary short and clearing to require you to replace some or all of your logic and analog circuits because reliability has been degraded.

So how did we solve this problem? For one thing, every digital and analog circuit had to be simulated with all combinations of power on/off sequencing and no part could be overstressed beyond limits set by reliability degradation. Then it had to be tested in the lab. For 24 hours in an oven cycled between minus 55 C and plus 125 C, the circuit had to survive all combination of sequencing, spending 24-hours in each partial sequenced state. It should come as no surprise that initially most circuits failed this requirement, but over time, circuit designers learned to design their circuits to pass this analysis and test criteria. It can be done, and when done, these circuits remained reliable even for more mundane events such as the momentary shorting of an IC across a bus with subsequent clearing, or a solder splash, or dropping a screwdriver into the computer circuit enclosure.

Another technique was the use of "housekeeping" power supplies that came on first and went off last and allowed the main power to be controlled by sensors and logic circuits.

Then, for the couple of critical circuits that required sequencing (less than one watt of circuits in a 300 W computer), the extraordinary circuit techniques needed to operate in this environment could be invoked and CRITICAL sequencing needs were met.

When you allow many circuits to require sequencing, you get into a catch-22 situation where one set of designers require system power to be sequenced in one combination and another set of designers require a different and incompatible sequencing. Often this is not discovered until the system is in final test or in the field. In the last year I have had calls from at least two engineers who were facing this problem only after shipping several units to the customer. The only solution to this besides requiring the circuit designers to redesign and do what they should have done in the first place (that is probably not going to happen) is to provide multiple power busses that can be individually sequenced. This results in a band-aid system design and complicates the recovery from latchup. When latchup occurs the normal (only?) remedy is to remove all power from the latched circuit immediately, often less than one or a few microseconds. When the carriers have cleared, you can reapply power. If this has to be done on multiple buses with sequencing requirements, things get difficult in a hurry.

Sneak paths are always a system problem and sequencing is often used as a solution but if used, it can conflict with other incompatible sequencing requirements and can result in system failure by failure of maintaining the proper sequencing. Sneak paths are such a problem that the military requires sneak path analysis along with reliability analysis before a system is approved.

The bottom line is to design your circuits and systems so they do not fail or degrade for any order of sequencing and use sequencing only for those function critical to the operation of your system.

The structure of the paper is:

• Introduction
• Why Sequence Power Supplies
  • Latch-Up
  • System-Level Bus Contention
• Sequencing Schemes
  • Sequential Sequencing
  • Ratio-Metric Sequencing
  • Simultaneous Sequencing
• Sequencing Implementations Illustrated with LDOs
  • Diodes
  • LDO Enable Via Supply Voltage Supervisor (SVS)
    • Sequential Sequencing
    • Simultaneous Sequencing
  • LDO and Power Distribution Switch
    • Sequential Sequencing
  • Hot-Swap Control
    • Simultaneous Sequencing
  • Microcontroller
    • Sequential Sequencing
• Sequencing with Switch-Mode Controllers, Converters, and Modules
  • Pre-Bias Start-Up and Synchronous Rectifiers
  • DC-DC Controllers
    • Ratio-Metric Sequencing
  • DC-DC Converters
    • Simultaneous Sequencing
    • Sequential Sequencing
    • Simultaneous Sequencing

The paper also discusses the special problem with synchronous rectifiers and the impact on power sequencing.

Here is the detailed bibliography information and abstract. After the 2004/05 seminar is complete it will probably appear on the Texas Instrument website. Until then you might be able to request a copy from the authors or a TI field engineer.

Reference: Daniels, David, Dirk Gehrke, and Mike Segal, Sequencing Power Supplies in Multiple Voltage Rail Environments, Texas Instruments 2004/05 Power Supply Design Seminar, SEM1600, pp. 2-1 to 2-31. 31 pages, 39 figures, 0 tables, 20 references, 4 appendices.

Author Abstract: Designers must consider timing and voltage differences during power up and power down in systems where multiple power rails are involved. A simple example would be a single DSP with its core and I/O voltages, requiring power supply sequencing. The possibility for a latch-up failure or excessive current draw exists when power supply sequencing is not designed properly. The trigger for latch-up may occur if power supplies are applied at different potentials of the core and I/O interfaces. This paper addresses some of the more common sequencing requirements of digital signal processing (DSPs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICSs) and microprocessors, and proposes a variety of practical solutions implemented with power management devices. These techniques take advantage of the reset, power good, enable and soft-start features available on many types of power management devices ranging from low drop out (LDO) regulators to plug-in power modules.

Posted by Jerrold Foutz